Minimal area sizing of power supply nets in VLSI circuits

The paper presents a simple dynamic programming approach to find minimum area sizings of power supply nets in VLSI circuits in time 𝒪((ℝA)²n), where n is the number of modules and ℝA is the difference between an upper bound of the area and the lower bound resulting from minimum feature size and electromigration constraints. This theoretical result makes it possible to develop efficient heuristic algorithms and to study their performance by experiments. A discussion of experimental results and extensions of the methods dealing with very large circuits are included.